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July 15 答辩结束 吼吼，DA的报告终于结束了。第一次用德语做报告，有胆量的尝试。 有朋友帮忙看了时间，正好25分钟。据说20到25分钟时间是比较合适的。上个礼拜第一次试讲的时候，拿着稿子念了46分钟，我自己念得都快睡着了。。。 第二次37分钟。。。 Michael的确很有耐心，非常热心的Betreuer，当时不但没有怨言，而且一个劲地鼓励我，帮我改稿子，真不知道该怎么感谢他。 今天的状况，说老实话，不是太满意。当然之前并没有太大期望，所以不存在失望，只是说要总结一下经验教训。 首先是发音吧。之前练习的时候有意识地进行了语音语调的练习，上午我自己一个人试讲的时候感觉也还不错。但是正式报告开始不到十分钟，感觉自己的语音语调有些奇怪，很别扭来着，越想纠正吧，就越是事与愿违（很想对听众说声对不起）。现在想想，还是平时功夫不到家。语言这个东西要靠平时积累，临时抱佛脚的下场会很难看的。改变的方法呢，先试试模仿吧，弄个耳麦话筒什么的，天天跟读那么几分钟，半年后看看会不会有什么意外的惊喜。以后做报告的场合不少呢，这个基本功很有必要。 注意力的持续时间也不太长。刚开始的时候还比较有感觉，看见ppt上的图立马能想到接下来该讲什么。不过不到十分钟，嘿嘿，就分散一部分到奇怪的发音上去了，到后半部分的时候脑子也迟钝了，再后来发现老爷子的脸上突然呈现出困惑的表情，于是又分散了一部分注意力去想老爷子为什么会困惑，发现是我把下一页的内容当成这一页讲了，当下就感觉后背一阵凉飕飕的。这个注意力分散的问题啊，不好说是怎么回事，难道和体力有关系么？ 寻求解答中。。。。 最不可以原谅的是，PPT上居然有拼写错误！之前Michael帮我改过几个单词，我也记得当时就马上纠正过来了，可这次居然又莫名其妙地出现了！他肯定特别失望啦，百忙之中抽空帮我改的，居然。。。希望他不要误会说我没有重视他的修改意见啊。这种低级错误啊，后悔开始之前没有在自习检查一下的。其实PPT自己就有拼写检查功能，而且那几个单词的确被检查出来了，可是我为什么没有在开始之前再自己看看哪，为什么为什么为什么！（看王牌大贱谍的朋友可以联想一下那两个永远步调不一致的助理主持人。。。） 报告的东西告一段落了，第一次德语做成这样也还好啦，以后有的是机会练习，不怕，嘿嘿，加油加油！ 接下来的任务就是写论文了，谁能相信我在一个礼拜之内能把80页的初稿从无到有的写出来呢？太不可能了，不过，试试看吧。 March 22 PCB1 ok第一块输入阻抗匹配的板子画好了，电路本身结构比较简单，画起来没有遇到太大的麻烦，当然 好不好用就要看老天的心情了。 第二块是数模转换板，算是高速电路数字电路和模拟电路的混合，感觉难度很大，动手之前还要好好修炼一下。希望半个月内，也就是4月5号之前能有一些想法并且开始动作。 加油加油，哇哈哈哈！ March 19 亮剑吧经过教授一说，发现我DA前面两个月有些地方考虑地不太周到，某些地方还走了弯路。 两个月过去了，进展不是很快，一方面是需要的软件还没有到位，另外一方面也是自己有些怠工。 初步估计有三块电路板要设计，有若干本书要读，困难不会少。 还是那句话，技术上没有过不去的坎，逢敌必亮剑，剑锋所指，所向披靡。亮剑吧！ January 19 Hard time for meHard time for me, I gotta turn to someone. All right, I have got two ideas about how the Hardware looks like, each has merit and demerit, and both might work, it's really not easy to decide, sometimes too many choices are worse than no choice.My dear Lord, please help me out! January 14 Theme of My Thesis"Design of a Modular Mixed-Signal Hardware Concept for PLC Channel Emulation" PLC Channel Emulation: It has the same conception as that I worked with in november, 2007. Modular: There will be several modules(in this context a module refers to a PCB) in my system, for example, a pure digital FPGA board named base board, a power supply module, several analog front end(AFE) modules, and several analog channel matching modules. Different modules have least superposition with each other, neither functionally nor physically. The modularization may provide enough flexibility, minimize workload when modifications are to be made in the system, and maximize the comfort to expansion of the system. The base board consists only of a FPGA, USB 2.0 interface(s), programming interface and high speed mezzanine connector(HSMC), it performs the most basic digital functions(such as digital signal processing, digital data transfer and so on) and is not application-oriented, so it can be used in different applications, and any modification of the whole system might not affect the basic board. The AFE module, as its name indicates, serves as the interface between digital and analogue worlds. There may be analog/digital converter(ADC), digital/analog converter(DAC), low-pass filter and interface to base board. the amount of AFE board depends on system configuration, for example, we may mount a ADC, a DAC and signal conditioning components on a PCB to define a AFE module which provides a communication participator with a transmit path and a receive paths. Each participator needs a AFE module to fulfill a duplex communication. The amount of AFE modules connected to the base board at the same time depends on how many participators there are. If more participators should be added later, all to do is just to connect the extra AFEs to the same base board, provided there are enough interfaces on the base board for new AFE modules. The channel matching module is the field where communiction participators take part in the communication scenario, it is the door to the thing(AFEs, base board), How exactly it looks like is out of my current bussiness, if I will get involved in it, depends... Add-in card2007-12-12
Aim: to check the performance of HSMC connection( data rate and signal
integrity issue ) and to gain practical experience with PCB design: December 11 2007/12/11 BreakpointQuartus II Version 7.1 Handbook
Page 5-84: Default I/O Timing and Power with Capacitive Loading. 2007/12/102007/12/10
What does DQ/DQS mean? Quartus II Version 7.1 Handbook, page 906; 2007/12/082007/12/08
How can I configure FPGA I/Os to LVDS, Single-ended...? December 05 2007-12-041. Get 5
HSMC sockets; 2. Installation of Starter kits CD: check! 3. Installation of USB Blaster driver: check! *** USB-Blaster Driver for Windows XP from Altera: http://www.altera.com/support/software/drivers/usb-blaster/dri-usb-blaster-xp.html 2007-12-04 You must install the Altera®
USB-Blaster™ download cable driver before you can use it to program devices
with Quartus® II software. 1. Plug the USB-Blaster into
the PC. The Found New Hardware Wizard appears. * Quartus II software version 6.1 and later: 1. Browse to the \x32 directory
(Windows 2000/XP standard 32-bit) or \x64 directory (Windows XP 64-bit). 1. Select the file usbblst.inf. 9. If the hardware Altera
USB-Blaster appears in the Model list, select the device. End*** 4. Break board for HSMC. At the very beginning, a PCB break board with HSMC headers mounted should be made to enable the access to HMSC pins. Although an add-on board is not optimal, it is the easiest way to work with HMSC. December 03 2007/12/03To do:
1. Get driver software installed; 2. Learn how to programe FPGA through external flash; 3. Learn how to configure FPGA I/Os to LVDS, Single-ended... 4. Get to know how to deal with the Mezzanine headers as well as the Connection of devboard to daughter card. November 30 Interfaces1. Got 5 HSMC Mezzanine headers today. However, only connectors, without dedicated cable! It would be really difficult to make such a cable dedicated for HSMC all by myself. Hey buddy, just image: the HSMC host socket on the devboard has totally 172 pins massing on a 5.6X0.57 cm2 aperture! Each pin should be connected to a conductor of the cable... Let me sit down for months, embroidering like a nanna? Over my dead body!
Of course you could work without cable. You could mount the Mezzanine header on a second board, we call it a daughter card. The daughter card then would be connected to the devboard by plugging the header into host socket. But, that is what Michael hates! That might lead to mechanical degradation after many times plugging in and plugging out.
2. The configuration of FPGA through USB interface can not be conducted until the USB-Blaster driver software is installed on host PC; We indeed have a USB interface on the devboard. However, that might be something differrent from the high speed communication between PC and FPGA, like that happens between USB sticks and PC. The USB interface is actually a part of the USB/JTAG adaptor for the programming of the on-board FPGA, with this adaptor, a PC is just a USB cable away from our devboard. Earlier, we employed a specific device named USB-Blaster programmer to download the bitstream file into FPGA. This kinda programmer is about three times bigger than a matchbox, whose one end is conneted to PC through a USB cable, the other side is plugged into a JTAG socket assembled on a FPGA board. Actually, this cute programmer is still in use everywhere. It is not bad, but might be not so popular with some guys: an extra device violates the spirit of integration and simplicity. To make live easier, Altera replaces the USB Blaster box with ICs and builds them on the same board as FPGA, instead of a USB-Blaster box, it is called USB-Blaster circuitry formally. According to the reference manual, the circuitry contains a FTDI FT2232L USB universal asynchronous receiver/transmitter(UART) circuit. The data from the FTDI chip is translated into a JTAG stream using the Altera EMP3128A CPLD connected to the FPGA's dedicated JTAG port. So, to gain a high speed data transfer with USB2.0, we need additional effort. :-( About the 12V DC supply to development boardAn adapter transforming 230V netz AC to a 12V DC provides the DC supply to development board (devboard). This adapter is connected to the development board(devboard) with a separated cable.
A concentric barrel DC connector(simply called connector) is fixed at one end of the cable, the matching socket is mounted on the devboard. In this way, the output of the connector provides the devboard with a DC supply. As to the connector, its outer conductor is the cathode, and inner connector the anode.
The adapter generates a 12V voltage between cathode and anode outputs. The other end of the cable, which is expect be inserted into the adapter, however, neither has a mark to tell which is anode and which is cathode, nor has any mechanical consideration to ensure the right polarity, i.e. if it is pluged into the adaptor correctly, the devboard gets the right +12V; However, it is also able to be inserted upside down into adapter due to the lack of mechanical consideration. As a result, a -12V will be supplied to development board, which can lead to a fatal damage to the devices on devboard.
Beware of wrong polarity! Confirm the right polarity with a multimeter before the connector is plugged into the devboard-socket. November 29 Milestone1. Get PC and CycloneIII Starter Kits;
2. Milestones:
A. Prototyp of a high speed base board;
1) Study the Development board, gotta be familiar with different components & devices,
esp. USB interface, HSMC and Power supply;
2) Learn circuit design with Eagle;
3) Design a prototype of base board with Cyclone III, USB interface(s) and HSMC connector;
B. Design of new channel emulator with multiple access operating under real PLC condition
(with sine ware of 230V, 50Hz) ; HSMC
1. what is clock-data-recovery transceiver? 2. Well, it would be better if there would be more figures. 3. What is the difference between COMS-, LVTTL-compatible I/O pins? 4. SMBUS: SMBUS is the System Management Bus defined by Intel Corporation in 1995. It is used in personal computer and servers for low-speed system management communications.--------- from http://smbus.org/ 5. 1 inch = 2.54e-2; http://www.themeter.net/conv7_e.htm 6. The specification is really beyond me currently. Gonna gnaw it again later.... |
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